org 0x0

start:
   mov r0,#0x53
   mov 0x20,#0x35
   
   ;anl a,Rn
   mov A,#0xE6
   ANL A,R0
   mov R1,A ; R1=0xE6 & 0x53
   
   ;anl A,direct
   mov a,#0xe7
   anl a,0x20
   mov r2,a  ;r2=0xe7 & 0x35
   
   ;anl a,@Ri
   mov A,#0xA4
   mov R0,#0x20
   ANL A,@R0
   mov R3,A ; R3=0xA4 & 0x35
   
   ;ANL A,#data
   mov A,#0x73
   ANL A,#0x64
   MOV R4,A
   
   ;ANL direct,A
   MOV A,#0xFc
   anl 0x20,A
   MOV R5,0x20  
   
   ;ANL direct, #data
   ANL 0x20,#0x76
   mov R6,0x20
   
   mov C,ACC.7
   anl C,0
   mov C,ACC.7
   ANL C,/ACC.7
   
   orl c,ACC.7
   anl C,0
   orl c,/acc.0
	sjmp $
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw 0x20,0x34
	dw REG_SP,    0x7
	dw REG_A,     0xfc
	dw REG_B,     0x0
	dw REG_PSW,   0x80
	dw REG_PC,    0x32
	dw REG_DPTR,  0x0
	dw CYCLE,     38
	dw REG_R0,    0x20
	dw REG_R1,    0x42
	dw REG_R2,    0x25
	dw REG_R3,    0x24
	dw REG_R4,    0x60
	dw REG_R5,    0x34
	dw REG_R6,    0x34
	dw REG_R7,    0x0
	dw REG_END
end
	